ADCs have widespread use in the field of communications and in audio, video and multimedia electronics. Much effort has been directed at improving the speed, accuracy and simplicity of ADCs.
Sigma-delta converters recently have come into widespread use. With relatively simple circuitry, sigma-delta converters achieve high accuracy. Sigma-delta technology employs oversampling-sampling at a rate greater than the Nyquist rate such that a majority of quantization noise (caused during conversion) is shifted to a frequency band greater than the signal bandwidth. The shift enables subsequent filtering of the noise. Sigma-delta technology thus enables high signal-to-noise ratios (SNRs). It also is compatible with CMOS processes.
In certain applications, such as multi-tone communications applications, for example, a need exists for ADCs with high accuracy (wide dynamic range) and high speed (wide bandwidth). To date, an ADC exhibiting wide dynamic range (e.g., &gt;80 dB) and wide bandwidth (e.g., &gt;200 kHz) has been difficult to achieve without employing complex and expensive circuitry.
Sigma-delta converters, by using oversampling techniques, typically exhibit wide dynamic range at the expense of limited bandwidth. Conversely, pipeline ADCs typically achieve wide bandwidth, but have limited dynamic range.
FIG. 1 is a block diagram showing a conventional pipeline converter including multiple stages S1, S2 and S3 cascade-connected together. Stages S1 and S2 consist of an ADC, a digital to-analog converter (DAC), and a subsequent residue amplifier (labeled AMP). These two stages of the pipeline provide an analog-to-digital conversion of the signal at the input of the stage and also provide an analog residue signal to the following stage. The last stage of the pipeline, stage S3, does not need to generate an analog residue signal to be used by a subsequent stage. Consequently stage S3 consists of a single ADC and does not include a DAC or a residue amplifier.
The first stage S1 consists of ADC1, DAC1, and AMP1. ADC1 receives an analog input voltage Vin and converts the input voltage to a digital code. DAC1 receives the digital code from ADC1 and converts this digital code back into an analog signal. AMP1 amplifies the difference between Vin and the analog signal at the output of DAC1 to provide an analog residue signal to the input of subsequent stage S2. The digital code from ADC1 also is provided to a digital pipeline correction logic block 10.
Stage S2 consists of ADC2, DAC2, and AMP2. ADC2 receives an input analog residue from stage S1 and converts the residue to a digital code. DAC2 receives the digital code from ADC2 and converts this digital code back into an analog signal. AMP2 amplifies the difference between the input analog residue signal and the analog signal at the output of DAC2 to provide an output analog residue signal to the input of subsequent stage S3. The digital code also is provided to logic 10. Stage S3 consists of ADC3. ADC3 receives an input analog residue from stage S2 and converts the residue to a digital code. Logic 10 time-aligns the digital codes from each stage and provides a digital output, representative of the analog input voltage Vin.
While each stage of the three-stage pipeline converter shown in FIG. 1 includes an ADC and may also include a DAC and an AMP, other circuit arrangements for each stage are known. For example, the AMP could be replaced by a sample-and-hold circuit. Alternatively, the residue amplification stage (the portion of each stage not including the ADC) could include a DAC, a differencer (adder/subtracter) and a residue amplifier.
The conversion rate of a pipeline converter, equal to the conversion time of a single stage of the pipeline, may be made very fast. The overall conversion time (required to process a single input sample), however, is equal to the sum of the conversion times of all of the stages. Consequently, typically there is a delay of several clock cycles from input to output of the pipeline converter. Additionally, the linearity of such converters is limited by element matching and inter-stage gain errors.
FIG. 2 is a block diagram showing a conventional single-bit sigma-delta ADC. As shown, the converter consists of an adder/subtractor 12, a loop filter 14, a one-bit ADC 16, a digital filter 20 and a one-bit DAC 18. An input is received by adder/subtractor 12 from which an error (provided by DAC 18) is subtracted. Loop filter 14 filters the difference and one-bit ADC 16 converts this signal to a digital signal. Errors are provided through the feedback path and converted by DAC 18. Digital filter 20 filters digital output samples to reduce quantization noise.
Such single-bit implementations are tolerant of element mismatch; linearity of the single-bit DAC circuitry in the modulator feedback loop is unaffected by element matching inaccuracy. A disadvantage associated with single-bit sigma-delta converters is that a large quantization error is produced by the single-bit quantizer (one-bit ADC 16) in the modulator loop. This degrades resolution and accuracy. Thus, high oversampling ratios (OSRs), typically 64 times or greater, are required to obtain wide dynamic range.
Higher-order modulator loops provide greater attenuation of noise within the signal bandwidth. High-order loops, however, are implemented at the expense of greater complexity and of reduced loop stability.
To increase the available signal bandwidth of sigma-delta modulators, either the sample rate of the modulator may be increased or the OSR may be reduced. Increased sample rates results in increased power consumption. Decreasing the OSR, on the other hand, directly reduces the improvements (such as reduced noise performance) obtained through oversampling.
To reduce the OSR while maintaining a given level of noise performance, it is necessary to provide additional reduction of in-band quantization noise. This may be achieved either through the use of a higher-order noise-shaping transfer function or through the use of increased quantizer resolution in a multi-bit sigma-delta modulator. The later option is preferable at low OSRs. Increased quantizer resolution results in a reduction of quantization noise throughout the entire spectrum. Higher-order noise-shaping transfer functions, on the other hand, provide reduction of quantization noise energy only within the signal bandwidth, and at low OSRs, they become less efficient at reducing in-band quantization noise.
The overall noise energy at the output of a modulator does not decrease with higher-order modulator loops. Higher-order noise-shaping transfer functions transfer more of the noise energy out-of-band where it may be reduced through digital filtering downstream of the modulator. For single-bit modulators operating at very low OSRs, the improvement (reduction) of in-band quantization noise is small as the loop order is increased. In contrast, the quantization noise of a multi-bit quantizer decreases greatly, at a rate of 6 dB per each additional bit of quantizer resolution, independent of the OSR or loop order.
One prior art approach aimed at reducing quantization noise is the so-called Mash sigma-delta architecture. Such an approach reduces quantization noise by increasing the order of the noise-shaping transfer function through the use of multiple modulator stages connected together (in a semi-cascade arrangement). An example of a Mash architecture is described in Oversampling Methods for A/D and D/A Conversion by Candy and Temes, which paper is herein incorporated by reference in its entirety.
In a Mash architecture, quantization errors of each modulator stage are processed in a following stage. Digital outputs of the stages are filtered and combined with outputs of previous stages in an attempt to cancel (or greatly reduce) the quantization errors of previous stages. Consequently, the quantization errors of all but the final stage in the Mash architecture are reduced in the combined digital output of the entire converter. A high-order noise-shaping transfer function may be achieved to maintain the quantization errors low in this final stage.
The advantage of the Mash architecture is that effectively, a high-order noise-shaping transfer function is achieved without employing a high-order loop. Rather, a multitude of independent low-order loops are connected to one another for this purpose. Stability problems associated with high-order loops therefore are avoided.
One disadvantage of the Mash architecture is that it is quite sensitive to matching accuracy of analog and digital processing circuits. Inaccuracies in analog element values (due, for examples, to manufacturing tolerance and to variations in temperature) cause errors in the analog modulator noise-shaping transfer functions. Mismatches result in improper cancellation or leakage of the quantization errors from the stages preceding the final stage of the converter into the digital output.
Matching accuracy becomes a more limiting problem as the overall order of the noise-shaping transfer function is increased in a Mash architecture through increasing the number of low-order stages. This results in smaller in-band quantization error energy associated with the final stage and, therefore, the output noise is more likely to be limited by imperfect cancellation of quantization errors in earlier stages.
Another approach at reducing quantization noise includes multi-bit sigma-delta converters. It has been shown that quantization noise may be reduced by approximately 6 dB per each additional bit of resolution in the quantizer. This reduction of noise with a multi-bit implementation is obtained without any corresponding increase in the OSR or loop order. Multi-bit techniques may be used to achieve a desired level of noise performance with a given (typically relatively low) OSR. Wide-bandwith sigma-delta converters commonly use the multi-bit approach to reduce oversampling requirements and thereby enable higher speed operation.
The multi-bit approach, however, suffers from serious drawbacks. It requires linear, accurate DAC circuitry in order to obtain high linearity and accuracy in the sigma-delta ADC. Errors in the DAC circuitry appear directly in the output code of the modulator. Consequently, the DAC circuitry must be as linear as that of the overall sigma-delta.
The stringent requirement of DAC linearity is difficult to achieve for most applications. Consequently, the performance of many prior art multi-bit sigma-delta ADCs is limited by the accuracy of the feedback DAC circuitry.
Truncation feedback multi-bit sigma-delta architecture is an approach that avoids the requirement of having a linear multi-bit DAC in the modulator loop. Such a truncated feedback multi-bit approach is described, for example, in An Improved Sigma-Delta Modulator Architecture by Leslie and Singh, which paper is herein incorporated by reference in its entirety.
This prior art approach uses a multi-bit quantizer and feeds only the most-significant bit (MSB) of the quantizer back in the modulator feedback loop. The n-bit digital output of the quantizer is divided into a one-bit MSB feedback signal and a separate n-1 bit feedforward signal, formed by the least-significant bits (LSBs) output by the quantizer. The LSBs are processed digitally and combined with the MSB in an attempt to cancel (or greatly reduce) the quantization error of the MSB signal, thereby improving the noise performance of the converter.
The digital signal provided with the LSBs provides a digital estimate of the single-bit quantization error of the MSB. To achieve cancellation (significant reduction) of the MSB quantization error, the LSBs are filtered using a digital filter having a digital transfer function that approximates the modulator noise-shaping transfer function. The LSBs, however, are limited in precision by the resolution and accuracy of the multi-bit quantizer. Consequently, the LSBs do not provide a perfect estimate of the large quantization error of the single-bit MSB.
The combined digital output signal of the truncation feedback arrangement provides a signal-to-noise ratio which is comparable to that of a conventional n-bit sigma-delta modulator but without incurring the non-linearity problems of a multi-bit feedback DAC.
A drawback of the truncation feedback architecture is that it suffers from the same sensitivity to matching of analog and digital transfer functions as does the Mash ADC architecture, described above. In order to fully cancel the quantization error in the MSB bit, the analog modulator noise-shaping transfer function must match (be an exact analog equivalent of) the transfer function of the digital filter used to process the LSB data. Inaccuracies in analog element values due to manufacturing tolerances and to variations in temperature typically result in an inaccurate modulator noise-shaping transfer function. This results in leakage of the MSB quantization error into the output of the converter. The noise performance therefore may be limited by matching accuracy. This becomes a greater problem when truncation feedback is used with a high-resolution quantizer. Increased quantizer resolution and accuracy results in a corresponding reduction of LSB quantization errors. As such, the noise is more dominated by leakage of the MSB quantization error.
Recent efforts to linearize multi-bit DAC circuitry have enabled new levels of performance by sigma-delta converters. As a result of this work, multi-bit sigma-delta converters are no longer necessarily limited by DAC linearity. Another constraint limiting the achievable performance of multi-bit sigma-delta ADCs, however, is a practical limit to resolution of the quantizer.
The noise reduction achieved with a multi-bit sigma-delta implementation depends on the number of bits in the quantizer. A large number of bits in the quantizer reduces the quantization noise. In order to obtain a large number of quantization bits, however, high resolution ADC and DAC converter circuitry must be employed in the modulator loop. This circuitry must be capable of quickly converting the analog and digital data. Any delays in the modulator loop must be small enough to avoid destabilizing the loop and degrading the filtering of in-band quantization noise.
A multi-bit quantizer implementation having a relatively fast conversion time includes the flash architecture. Unfortunately, the number of comparators in this architecture grows exponentially as the number of bits is increased. As such, the flash architecture is undesirable for use in high-resolution quantizers because the size and power of the ADC implementation doubles for each additional bit of resolution. Alternative quantizer implementations may provide more efficient circuit implementations at the expense of requiring increased conversion time (the overall length of time required to convert the signal). Such ADC circuit implementations typically are made efficient through repetitive processing of the analog signal. Conversion time with such implementations is inherently larger than that of a single flash ADC because several steps are required to obtain the final answer, as described above with reference to the pipeline converter shown in FIG. 1.
Practical implementations of flash ADCs commonly are limited to a maximum of five to eight bits. Therefore, multi-bit sigma-delta ADC implementations also typically are limited to quantizer resolutions of less than eight bits. This limits the minimum value of the OSR that can be used with a multi-bit sigma-delta ADC to achieve a given level of noise performance. OSRs in the range of 32.times. to 128.times. typically are used with multi-bit sigma-delta ADCs.
It is a general object of the present invention to provide a high speed, high accuracy ADC that avoids the drawbacks of the prior art.